The present invention relates to an asynchronous transfer mode (ATM) switch in which information switching is accomplished in a unit of cells or to an ATM switch and a method of controlling the same in an ATM cross-connection system.
In an ATM switch of the prior art, each ATM cell is assigned with a routing tag so as to be routed depending on the routing tag.
As stiplulated in the CCITT Recommendation 1.432, an ATM cell is 53 bytes long. In operation inside the ATM switch, a routing tag is added thereto such that an ATM cell in the switch includes 54 to 64 bytes. The ATM cell has a period or cycle of about 44 cells for each 125 microseconds (.mu.s) in a 150 Mb/s operation. For example, an ATM switch processing about 2800 cells in each 125 .mu.s (equivalent to 150 Mb/s.times.64 lines) has a switching capacity of about 10 Gb/s. In this conventional technology, when configuring an ATM switch of such a large capacity, a plurality of unitary switch LSIs are arranged in a two-dimensional structure. Such an ATM switch has been described, for example, in an article "Development of ATM Switch LSIs for Broadband ISDN" written by J. Kamoi et al. in the Proceedings of 1990 Spring Convention of IEICE of Japan, B-443 (Mar. 18, 1990), p. 3-21. Specifically, 64 one-chip LSIs each including an 8.times.8 switch (150 Mb/s) are arranged in a two-dimensional constitution to construct a 64.times.64 switch (150 Mb/s).
In the ATM switch of the prior art, since each ATM cell is routed by use of a routing tag assigned thereto, the ATM cell is switched together with the routing tag in any situation. Consequently, the switching capacity of the unitary ATM switch is restricted by the size of a hardware system of the switch to be mounted in a one-chip LSI and the signal capacity i.e. the maximum number of input/output signals to be processed by the one-chip LSI. In order to improve the performance of the switch, the unitary switches are required to be configured in a two-dimensional form as described above. However, this is attended with a problem that the hardware size increases in proportion to a square of the switch capacity.
Meanwhile, JP-A-2-2767 (laid-open on Jan. 8, 1990) corresponding to DE-A-3742941 shows a packet switch system having input devices, one provided between a switch and each of inputs, in which the input devices serve to divide packets into sub-packets.